66 search results - page 2 / 14 » Masking timing errors on speed-paths in logic circuits |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
DSN
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...