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ASPDAC
2010
ACM
124views Hardware» more  ASPDAC 2010»
13 years 2 months ago
MuCCRA-3: a low power dynamically reconfigurable processor array
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tun...
FPL
2008
Springer
129views Hardware» more  FPL 2008»
13 years 6 months ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
IPPS
1998
IEEE
13 years 9 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl...
JCP
2007
154views more  JCP 2007»
13 years 4 months ago
Partially Reconfigurable Vector Processor for Embedded Applications
—Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, a...
Muhammad Z. Hasan, Sotirios G. Ziavras
GLOBECOM
2007
IEEE
13 years 6 months ago
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
Min Li, Bruno Bougard, Eduardo Lopez-Estraviz, And...