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DATE
1997
IEEE
76views Hardware» more  DATE 1997»
13 years 9 months ago
New static compaction techniques of test sequences for sequential circuits
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
ATS
1998
IEEE
76views Hardware» more  ATS 1998»
13 years 9 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
VTS
1997
IEEE
96views Hardware» more  VTS 1997»
13 years 9 months ago
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 8 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 9 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...