8 search results - page 1 / 2 » New timing and routability driven placement algorithms for F... |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
TCAD
2008
13 years 4 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...