—Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particular...
Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Bec...
High resistance bridges (resistive bridges) are becoming more common. Such bridges cause speed failures. Published experimental results show that current tests are not good at det...
Delay defects can escape detection during the normal production test flow, particularly if they do not affect any of the long paths included in the test flow. Some defect types ca...
Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao...
We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detec...
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...