Sciweavers

36 search results - page 3 / 8
» On generating compact test sequences for synchronous sequent...
Sort
View
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
13 years 10 months ago
An approach for improving the levels of compaction achieved by vector omission
We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are ...
Irith Pomeranz, Sudhakar M. Reddy
ATS
1998
IEEE
76views Hardware» more  ATS 1998»
13 years 10 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
DATE
1997
IEEE
76views Hardware» more  DATE 1997»
13 years 10 months ago
New static compaction techniques of test sequences for sequential circuits
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
DATE
2003
IEEE
114views Hardware» more  DATE 2003»
13 years 11 months ago
A New Approach to Test Generation and Test Compaction for Scan Circuits
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
13 years 9 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar