79 search results - page 2 / 16 » Place and Route for Secure Standard Cell Design |
DATE
2007
IEEE
13 years 12 months ago
2007
IEEE
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
ISVLSI
2008
IEEE
13 years 12 months ago
2008
IEEE
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
The thermal problem has been emerged as one of the key issues for next-generation IC design. In this paper, we propose a scheme to achieve better thermal distribution for partitio...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
SOCC
2008
IEEE
13 years 12 months ago
2008
IEEE
Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapa...