51 search results - page 2 / 11 » Process Variation Tolerant 3T1D-Based Cache Architectures |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...