55 search results - page 1 / 11 » Reconfigurable scan chains: a novel approach to reduce test ... |
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
