33 search results - page 2 / 7 » Register placement for high-performance circuits |
ARVLSI
1999
IEEE
13 years 9 months ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...