33 search results - page 3 / 7 » Register placement for high-performance circuits |
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...