74 search results - page 2 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
ETS
2009
IEEE
13 years 3 months ago
2009
IEEE
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
AIA
2007
13 years 6 months ago
2007
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...