13 search results - page 1 / 3 » Scan Power Reduction Through Test Data Transition Frequency ... |
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
ICCD
2003
IEEE
13 years 10 months ago
2003
IEEE
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
DFT
2002
IEEE
13 years 9 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...