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» System-level power estimation and optimization
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DATE
1998
IEEE
141views Hardware» more  DATE 1998»
13 years 8 months ago
Address Bus Encoding Techniques for System-Level Power Optimization
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
Luca Benini, Giovanni De Micheli, Donatella Sciuto...
CF
2005
ACM
13 years 6 months ago
Power and performance optimization at the system level
Valentina Salapura, Randy Bickford, Matthias A. Bl...
DAC
1997
ACM
13 years 8 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak
TVLSI
2010
12 years 11 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
13 years 11 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...