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» Technology mapping for domino logic
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ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
13 years 10 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
ISCAS
2006
IEEE
135views Hardware» more  ISCAS 2006»
13 years 11 months ago
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
Volkan Kursun, Zhiyu Liu
ISQED
2006
IEEE
132views Hardware» more  ISQED 2006»
13 years 11 months ago
Leakage Biased Sleep Switch Domino Logic
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
Zhiyu Liu, Volkan Kursun
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
13 years 9 months ago
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 5 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal