77 search results - page 1 / 16 » Test Generation for Global Delay Faults |
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the numbe...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 2 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...