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» Through Silicon Vias as Enablers for 3D Systems
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DATE
2009
IEEE
154views Hardware» more  DATE 2009»
14 years 11 days ago
Reliability aware through silicon via planning for 3D stacked ICs
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kua...
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
14 years 13 days ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
ICCAD
2009
IEEE
129views Hardware» more  ICCAD 2009»
13 years 3 months ago
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
13 years 10 months ago
3D-integration of silicon devices: A key technology for sophisticated products
—3D integration is a key solution to the predicted performance increase of future electronic systems. It offers extreme miniaturization and fabrication of More than Moore product...
Armin Klumpp, Peter Ramm, R. Wieland
VLSI
2010
Springer
13 years 4 months ago
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
Fengda Sun, Alessandro Cevrero, Panagiotis Athanas...