58 search results - page 3 / 12 » Timing driven power gating in high-level synthesis |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
TCAD
2008
13 years 5 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...