10 search results - page 2 / 2 » Total power reduction in CMOS circuits via gate sizing and m... |
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
DAC
2008
ACM
13 years 6 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...