18 search results - page 3 / 4 » Transistor reordering rules for power reduction in CMOS gate... |
PATMOS
2007
Springer
13 years 11 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
ISVLSI
2005
IEEE
13 years 11 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
TCAD
2008
13 years 5 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
DATE
2009
IEEE
14 years 2 days ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...