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ASPDAC
2005
ACM
110views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Compact and stable modeling of partial inductance and reluctance matrices
Abstract— The sparsification of the reluctance matrix L−1 (where L denotes the usual inductance matrix L) has been widely used in several recent investigations to make the pro...
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Ko...
ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-...
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 6 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Power estimation starategies for a low-power security processor
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling C...
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Process variation robust clock tree routing
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
Wai-Ching Douglas Lam, Cheng-Kok Koh
ASPDAC
2005
ACM
116views Hardware» more  ASPDAC 2005»
13 years 6 months ago
A flexible framework for communication evaluation in SoC design
— We present SoCExplore, a framework for fast communicationcentric design space exploration of complex SoCs with networkbased interconnects. Speed-up in exploration is achieved t...
Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Standard CMOS technology on-chip inductors with pn junctions substrate isolation
New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the re...
Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, M...
ASPDAC
2005
ACM
91views Hardware» more  ASPDAC 2005»
13 years 6 months ago
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem
-- This paper presents a novel global routing algorithm, AT-PO-GR, to minimize the routing area under both congestion, timing, and RLC crosstalk constraints. The proposed algorithm...
Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, ...
ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
ASPDAC
2005
ACM
96views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Comprehensive frequency dependent interconnect extraction and evaluation methodology
Abstract— Frequency dependent interconnect analysis is challenging since lumped equivalent circuit models extracted at different frequencies exhibit distinct time and frequency d...
Rong Jiang, Charlie Chung-Ping Chen