Sciweavers

ASPDAC
2006
ACM
159views Hardware» more  ASPDAC 2006»
13 years 10 months ago
An anytime symmetry detection algorithm for ROBDDs
Neil Kettle, Andy King
ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A probabilistic analysis of pipelined global interconnect under process variations
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
Navneeth Kankani, Vineet Agarwal, Janet Meiling Wa...
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Maximizing data reuse for minimizing memory space requirements and execution cycles
Mahmut T. Kandemir, Guangyu Chen, Feihui Li
ASPDAC
2006
ACM
103views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Prefetching-aware cache line turnoff for saving leakage energy
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...
Ismail Kadayif, Mahmut T. Kandemir, Feihui Li
ASPDAC
2006
ACM
99views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Finding optimal L1 cache configuration for embedded systems
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
ASPDAC
2006
ACM
102views Hardware» more  ASPDAC 2006»
13 years 10 months ago
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
— Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the numbe...
Zhuo Li, Weiping Shi
ASPDAC
2006
ACM
126views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A novel instruction scratchpad memory optimization method based on concomitance metric
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated tha...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
13 years 10 months ago
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices
We present a technique for the fast and accurate simulation of largescale VLSI interconnects with nonlinear devices, called SASIMI. The numerical efficiency of this technique is ...
Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkat...
ASPDAC
2006
ACM
153views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Diagonal routing in high performance microprocessor design
This paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan rout...
Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita,...
ASPDAC
2006
ACM
155views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Delay defect screening for a 2.16GHz SPARC64 microprocessor
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to...
Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hito...