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ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Area optimization for leakage reduction and thermal stability in nanometer scale technologies
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
Ja Chun Ku, Yehea I. Ismail
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
13 years 10 months ago
High-throughput decoder for low-density parity-check code
— We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regula...
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Iken...
ASPDAC
2006
ACM
93views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Open access overview "industrial experience"
- Renesas Technology Corp. designers turned to OpenAccess to address the major design challenges with systems on chip for the automotive, wireless, digital consumer and industrial ...
Yoshio Inoue
ASPDAC
2006
ACM
98views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Timing-driven placement based on monotone cell ordering constraints
− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed th...
Chanseok Hwang, Massoud Pedram
ASPDAC
2006
ACM
176views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Conversion of reference C code to dataflow model: H.264 encoder case study
– Model-based design is widely accepted in developing complex embedded system under intense time-to-market pressure. While it promises improved design productivity, the main bott...
Hyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi H...
ASPDAC
2006
ACM
90views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A routability constrained scan chain ordering technique for test power reduction
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
X.-L. Huang, J.-L. Huang
ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Fast multi-domain clock skew scheduling for peak current reduction
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
ASPDAC
2006
ACM
110views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Switching-activity driven gate sizing and Vth assignment for low power design
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
ASPDAC
2006
ACM
144views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
Abstract— Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored...
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahas...
ASPDAC
2006
ACM
124views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Functional modeling techniques for efficient SW code generation of video codec applications
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya