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ASPDAC
2007
ACM
96views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Novel Performance-Driven Topology Design Algorithm
This paper presents a very efficient algorithm for performance-driven topology design for interconnects. Given a net, it first generates A-tree1 topology using table lookup and net...
Min Pan, Chris C. N. Chu, Priyadarshan Patra
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Fast Analytic Placement using Minimum Cost Flow
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
Ameya R. Agnihotri, Patrick H. Madden
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
- For sub-90nm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/So...
Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvi...
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Run-Time Memory Protection Methodology
Udaya Seshua, Nagaraju Bussa, Bart Vermeulen
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
ASPDAC
2007
ACM
91views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
ASPDAC
2007
ACM
80views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Recognition of Fanout-free Functions
Factoring is a logic minimization technique to represent a Boolean function in an equivalent function with minimum literals. When realizing the circuit, a function represented in ...
Tsung-Lin Lee, Chun-Yao Wang
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Fast Buffer Insertion for Yield Optimization Under Process Variations
With the emerging process variations in fabrication, the traditional corner-based timing optimization techniques become prohibitive. Buffer insertion is a very useful technique fo...
Ruiming Chen, Hai Zhou
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...