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ICPP
2009
IEEE
8 years 10 months ago
Cache-Efficient, Intranode, Large-Message MPI Communication with MPICH2-Nemesis
The emergence of multicore processors raises the need to efficiently transfer large amounts of data between local processes. MPICH2 is a highly portable MPI implementation whose l...
Darius Buntinas, Brice Goglin, David Goodell, Guil...
HIPC
2009
Springer
8 years 10 months ago
Non-uniform power access in large caches with low-swing wires
Modern processors dedicate more than half their chip area to large L2 and L3 caches and these caches contribute significantly to the total processor power. A large cache is typica...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...
HIPC
2009
Springer
8 years 10 months ago
Distance-aware round-robin mapping for large NUCA caches
In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-...
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, Jos...
ECRTS
2009
IEEE
8 years 10 months ago
Using Randomized Caches in Probabilistic Real-Time Systems
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access p...
Eduardo Quiñones, Emery D. Berger, Guillem ...
ANCS
2009
ACM
8 years 10 months ago
EINIC: an architecture for high bandwidth network I/O on multi-core processors
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve...
MICRO
2010
IEEE
132views Hardware» more  MICRO 2010»
8 years 10 months ago
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very ...
Timothy N. Miller, Renji Thomas, James Dinan, Bruc...
MICRO
2010
IEEE
146views Hardware» more  MICRO 2010»
8 years 10 months ago
The ZCache: Decoupling Ways and Associativity
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
Daniel Sanchez, Christos Kozyrakis
ISW
2010
Springer
8 years 10 months ago
An Analysis of DepenDNS
Recently, a new scheme to protect clients against DNS cache poisoning attacks was introduced. The scheme is referred to as DepenDNS and is intended to protect clients against such ...
Nadhem J. AlFardan, Kenneth G. Paterson
IPPS
2010
IEEE
8 years 10 months ago
Exploiting inter-thread temporal locality for chip multithreading
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize ...
Jiayuan Meng, Jeremy W. Sheaffer, Kevin Skadron
IPPS
2010
IEEE
8 years 10 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...
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