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CODES
2005
IEEE
9 years 3 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
CF
2006
ACM
9 years 3 months ago
Intermediately executed code is the key to find refactorings that improve temporal data locality
The growing speed gap between memory and processor makes an efficient use of the cache ever more important to reach high performance. One of the most important ways to improve cac...
Kristof Beyls, Erik H. D'Hollander
CF
2005
ACM
9 years 3 months ago
Controlling leakage power with the replacement policy in slumberous caches
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is diss...
Nasir Mohyuddin, Rashed Bhatti, Michel Dubois
CCS
2008
ACM
9 years 3 months ago
Deconstructing new cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks present a serious threat to computer systems. Previously proposed countermeasures were either too costly for practical use or only effect...
Jingfei Kong, Onur Aciiçmez, Jean-Pierre Se...
CASES
2008
ACM
9 years 3 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
ASPLOS
2008
ACM
9 years 3 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
FAST
2008
9 years 3 months ago
TaP: Table-based Prefetching for Storage Caches
TaP is a storage cache sequential prefetching and caching technique to improve the read-ahead cache hit rate and system response time. A unique feature of TaP is the use of a tabl...
Mingju Li, Elizabeth Varki, Swapnil Bhatia, Arif M...
CASES
2009
ACM
9 years 4 months ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
ASPLOS
1991
ACM
9 years 5 months ago
The Cache Performance and Optimizations of Blocked Algorithms
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...
Monica S. Lam, Edward E. Rothberg, Michael E. Wolf
PLDI
1995
ACM
9 years 5 months ago
Tile Size Selection Using Cache Organization and Data Layout
When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for ch...
Stephanie Coleman, Kathryn S. McKinley
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