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DAC
2004
ACM
9 years 9 months ago
A timing-driven module-based chip design flow
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
Fan Mo, Robert K. Brayton
DAC
2004
ACM
9 years 9 months ago
Optical proximity correction (OPC): friendly maze routing
As the technology migrates into the deep submicron manufacturing (DSM) era, the critical dimension of the circuits is getting smaller than the lithographic wavelength. The unavoid...
Li-Da Huang, Martin D. F. Wong
DAC
2004
ACM
9 years 9 months ago
Low voltage swing logic circuits for a Pentium 4 processor integer core
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
Daniel J. Deleganes, Micah Barany, George Geannopo...
DAC
2004
ACM
9 years 9 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
DAC
2004
ACM
9 years 9 months ago
Correct-by-construction layout-centric retargeting of large analog designs
Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. The strong impact of layout intricacies on analog circuit performance n...
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy ...
DAC
2004
ACM
9 years 9 months ago
Fast and accurate parasitic capacitance models for layout-aware
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tabl...
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanch...
DAC
2004
ACM
10 years 4 months ago
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...
Chong Zhao, Xiaoliang Bai, Sujit Dey
DAC
2004
ACM
10 years 4 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
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