Sciweavers

DAC
2009
ACM
14 years 5 months ago
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power c...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
DAC
2009
ACM
14 years 5 months ago
An SDRAM-aware router for Networks-on-Chip
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...
Wooyoung Jang, David Z. Pan
DAC
2009
ACM
14 years 5 months ago
An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems
? In this paper we propose an adaptive scheduling and voltage/frequency selection algorithm which targets at energy harvesting systems. The proposed algorithm adjusts the processor...
Shaobo Liu, Qing Wu, Qinru Qiu
DAC
2009
ACM
14 years 5 months ago
A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction
State-of-the-art integral-equation-based solvers rely on techniques that can perform a matrix-vector multiplication in O(N) complexity. In this work, a fast inverse of linear comp...
Wenwen Chai, Dan Jiao, Cheng-Kok Koh
DAC
2009
ACM
14 years 5 months ago
A real-time program trace compressor utilizing double move-to-front method
This paper introduces a new unobtrusive and cost-effective method for the capture and compression of program execution traces in real-time, which is based on a double move-to-fron...
Vladimir Uzelac, Aleksandar Milenkovic
DAC
2009
ACM
14 years 5 months ago
Optimal static WCET-aware scratchpad allocation of program code
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...
Heiko Falk, Jan C. Kleinsorge
DAC
2009
ACM
14 years 5 months ago
WCET-aware register allocation based on graph coloring
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the...
Heiko Falk
DAC
2009
ACM
14 years 5 months ago
Fault models for embedded-DRAM macros
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
Ching-Yu Chin, Hao-Yu Yang, Mango Chia-Tso Chao, R...
DAC
2009
ACM
14 years 5 months ago
On systematic illegal state identification for pseudo-functional testing
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
Feng Yuan, Qiang Xu
DAC
2009
ACM
14 years 5 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...