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DATE
1999
IEEE
92views Hardware» more  DATE 1999»
9 years 4 months ago
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
Peter Feldmann, Sharad Kapur, David E. Long
DATE
1999
IEEE
105views Hardware» more  DATE 1999»
9 years 4 months ago
Identification and Exploitation of Symmetries in DSP Algorithms
In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit thes...
C. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman...
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
9 years 4 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
DATE
1999
IEEE
64views Hardware» more  DATE 1999»
9 years 4 months ago
Dynamic Power Management for non-stationary service requests
Dynamic Power Management is a design methodology aiming at reducing power consumption of electronic systems, by performing selective shutdown of the idle system resources. The eff...
Eui-Young Chung, Luca Benini, Alessandro Bogliolo,...
DATE
1999
IEEE
66views Hardware» more  DATE 1999»
9 years 4 months ago
Specification and Validation of Distributed IP-Based Designs with JavaCAD
Marcello Dalpasso, Alessandro Bogliolo, Luca Benin...
DATE
1999
IEEE
144views Hardware» more  DATE 1999»
9 years 4 months ago
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester
This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behavior in a fir...
Érika F. Cota, Luigi Carro, Marcelo Lubasze...
DATE
1999
IEEE
138views Hardware» more  DATE 1999»
9 years 4 months ago
Codex-dp: Co-design of Communicating Systems Using Dynamic Programming
We present a novel algorithm based on dynamic programming with binning to find, subject to a given deadline, the minimum-cost coarse-grain hardware/software partitioning and mappin...
Jui-Ming Chang, Massoud Pedram
DATE
1999
IEEE
89views Hardware» more  DATE 1999»
9 years 4 months ago
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement
Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The p...
Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge...
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
9 years 4 months ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...
DATE
1999
IEEE
86views Hardware» more  DATE 1999»
9 years 4 months ago
Glitch Power Minimization by Gate Freezing
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
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