DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We present an approach to bus access optimization and schedulability analysis for the synthesis of hard real-time distributed embedded systems. The communication model is based on...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper in...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
