DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints. We use mini...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
: We address the issue of standards development for the system-level design space. System-level design IP re-use standards are key to the future of the VSIA. However, the concept o...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
The widespread adoption of embedded microprocessor-based systems for safety critical applications mandates the use of co-design tools able to evaluate system dependability at ever...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Embedded systems make a heavy use of software to perform Real-Time embedded control tasks. Embedded software is characterized by a relatively long lifetime and by tight cost, perf...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE