DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. For high-spee...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper presents an efficient approach to compute the dominant poles for the reduced-order admittance (Y parameter) matrix of lossy interconnects. Using the global approximati...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper explores the role of data analysis methods to support system-level designers in characterising the performance of embedded applications. In particular, we address the p...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
The core computation in BDD-based symbolic synthesis and verification is forming the image and pre-image of sets of states under the transition relation characterizing the sequen...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE