Sciweavers

DATE
2002
IEEE
89views Hardware» more  DATE 2002»
13 years 9 months ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
13 years 9 months ago
Reconfigurable SoC - What Will it Look Like?
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chri...
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
13 years 9 months ago
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael ...
DATE
2002
IEEE
169views Hardware» more  DATE 2002»
13 years 9 months ago
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics
There are some types of faults in analogue and mixed signal circuits which are very difficult to detect using either voltage or current based test methods. However, it is possible...
Yolanda Lechuga, Román Mozuelos, Mar Mart&i...
DATE
2002
IEEE
112views Hardware» more  DATE 2002»
13 years 9 months ago
Global Optimization Applied to the Oscillator Problem
The oscillator problem consists of determining good initial values for the node voltages and the frequency of oscillation and the avoidance of the DC solution. Standard approaches...
S. Lampe, S. Laur
DATE
2002
IEEE
117views Hardware» more  DATE 2002»
13 years 9 months ago
Effective Software Self-Test Methodology for Processor Cores
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning tech...
Nektarios Kranitis, Antonis M. Paschalis, Dimitris...
DATE
2002
IEEE
156views Hardware» more  DATE 2002»
13 years 9 months ago
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
Chris H. Kim, Kaushik Roy
DATE
2002
IEEE
81views Hardware» more  DATE 2002»
13 years 9 months ago
A Two-Tier Distributed Electronic Design Framework
Tom J. Kazmierski, Neil Clayton
DATE
2002
IEEE
104views Hardware» more  DATE 2002»
13 years 9 months ago
A Compiler-Based Approach for Improving Intra-Iteration Data Reuse
Intra-iteration data reuse occurs when multiple array references exhibit data reuse in a single loop iteration. An optimizing compiler can exploit this reuse by clustering (in the...
Mahmut T. Kandemir
DATE
2002
IEEE
101views Hardware» more  DATE 2002»
13 years 9 months ago
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization
This paper presents a novel Energy-Aware Compilation (EAC) framework that can estimate and optimize energy consumption of a given code taking as input the architectural and techno...
Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vija...