DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
The key performance of many analog circuits is directly related to accurate capacitor ratios. It is well known that capacitor ratio precision is greatly enhanced by paralleling id...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced crosstalk noise for distributed RC coupling trees. The efficiency of our approach...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the considerati...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Although algorithm level re-computing techniques can trade-off the detection capability of Concurrent Error Detection (CED) vs. time overhead, it results in 100% time overhead whe...