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DATE
2004
IEEE
152views Hardware» more  DATE 2004»
13 years 8 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
DATE
2004
IEEE
133views Hardware» more  DATE 2004»
13 years 8 months ago
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration...
Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 8 months ago
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...
Mounir Benabdenbi, Alain Greiner, François ...
DATE
2004
IEEE
127views Hardware» more  DATE 2004»
13 years 8 months ago
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
M. Bellato, Paolo Bernardi, D. Bortolato, A. Cande...
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
13 years 8 months ago
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
Paolo Bernardi, Guido Masera, Federico Quaglio, Ma...
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 8 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
DATE
2004
IEEE
128views Hardware» more  DATE 2004»
13 years 8 months ago
Enhanced Diameter Bounding via Structural
Bounded model checking (BMC) has gained widespread industrial use due to its relative scalability. Its exhaustiveness over all valid input vectors allows it to expose arbitrarily ...
Jason Baumgartner, Andreas Kuehlmann
DATE
2004
IEEE
185views Hardware» more  DATE 2004»
13 years 8 months ago
Energy-Aware System Design for Wireless Multimedia
In this paper, we present various challenges that arise in the delivery and exchange of multimedia information to mobile devices. Specifically, we focus on techniques for maintain...
Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta...
DATE
2004
IEEE
123views Hardware» more  DATE 2004»
13 years 8 months ago
On Concurrent Error Detection with Bounded Latency in FSMs
We discuss the problem of concurrent error detection (CED) with bounded latency in finite state machines (FSMs). The objective of this approach is to reduce the overhead of CED, a...
Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris