Sciweavers

FPL
2005
Springer
98views Hardware» more  FPL 2005»
13 years 11 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
13 years 11 months ago
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations
Carlos Morra, Jürgen Becker, Mauricio Ayala-R...
FPL
2005
Springer
114views Hardware» more  FPL 2005»
13 years 11 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...
FPL
2005
Springer
140views Hardware» more  FPL 2005»
13 years 11 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
FPL
2005
Springer
96views Hardware» more  FPL 2005»
13 years 11 months ago
FPGA PLB Evaluation using Quantified Boolean Satisfiability
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
FPL
2005
Springer
226views Hardware» more  FPL 2005»
13 years 11 months ago
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...
FPL
2005
Springer
125views Hardware» more  FPL 2005»
13 years 11 months ago
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
Marco Lanuzza, Stefania Perri, Martin Margala, Pas...
FPL
2005
Springer
100views Hardware» more  FPL 2005»
13 years 11 months ago
HAIL: A Hardware-Accelerated Algorithm for Language Identification
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
FPL
2005
Springer
121views Hardware» more  FPL 2005»
13 years 11 months ago
Configuration Merging for Adaptive Computer Applications
We present experimental evidence that multiple compute-units, compiled from sequential high-level language input programs, can be merged into a reduced number of configurations f...
Nico Kasprzyk, Jan van der Veen, Andreas Koch
FPL
2005
Springer
98views Hardware» more  FPL 2005»
13 years 11 months ago
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
Peter Jamieson, Jonathan Rose