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ASYNC
2010
IEEE
230views Hardware» more  ASYNC 2010»
8 years 5 months ago
The Devolution of Synchronizers
— Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the ...
Salomon Beer, Ran Ginosar, Michael Priel, Rostisla...
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
9 years 3 months ago
Analytical model for the impact of multiple input switching noise on timing
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraha...
ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
9 years 5 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
9 years 6 months ago
Shielding effect of on-chip interconnect inductance
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
Magdy A. El-Moursy, Eby G. Friedman
GLVLSI
2006
IEEE
113views VLSI» more  GLVLSI 2006»
9 years 7 months ago
Statistical gate delay calculation with crosstalk alignment consideration
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
Andrew B. Kahng, Bao Liu, Xu Xu
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
9 years 7 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
VTS
2007
IEEE
95views Hardware» more  VTS 2007»
9 years 7 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
10 years 1 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
DAC
2000
ACM
10 years 2 months ago
Convex delay models for transistor sizing
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapat...
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