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MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
9 years 1 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
9 years 1 months ago
Instruction Set Emulation for Rapid Prototyping of SoCs
In this paper the application of Instruction Set Emulation for rapid prototyping of SoCs will be presented. The emulation works in a way that both the software and the hardware be...
Jürgen Schnerr, Gunter Haug, Wolfgang Rosenst...
DATE
2003
IEEE
102views Hardware» more  DATE 2003»
9 years 1 months ago
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer
: A modern special-purpose processor (e.g., for image and graphical applications) usually contains a set of instructions supporting complex multiply-operations. These instructions ...
Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingT...
CGO
2003
IEEE
9 years 1 months ago
Dynamic Binary Translation for Accumulator-Oriented Architectures
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
Ho-Seop Kim, James E. Smith
LCTRTS
2004
Springer
9 years 1 months ago
Feedback driven instruction-set extension
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael ...
CASES
2006
ACM
9 years 2 months ago
Code transformation strategies for extensible embedded processors
Embedded application requirements, including high performance, low power consumption and fast time to market, are uncommon in the broader domain of general purpose applications. I...
Paolo Bonzini, Laura Pozzi
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
9 years 2 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
IPPS
2006
IEEE
9 years 2 months ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
9 years 2 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
ACSAC
2006
IEEE
9 years 2 months ago
Known/Chosen Key Attacks against Software Instruction Set Randomization
Instruction Set Randomization (ISR) has been proposed as a form of defense against binary code injection into an executing program. One proof-of-concept implementation is Randomiz...
Yoav Weiss, Elena Gabriela Barrantes
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