Sciweavers

ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
14 years 2 months ago
A thread partitioning algorithm in low power high-level synthesis
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Ta...
IPSN
2005
Springer
14 years 2 months ago
XYZ: a motion-enabled, power aware sensor node platform for distributed sensor network applications
— This paper describes the XYZ, a new open-source sensing platform specifically designed to support our experimental research in mobile sensor networks. The XYZ node is designed...
Dimitrios Lymberopoulos, Andreas Savvides
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 2 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ISCAS
2005
IEEE
141views Hardware» more  ISCAS 2005»
14 years 2 months ago
A low voltage CMOS multiplier for high frequency equalization
- This paper describes the design of a low power
Justin P. Abbott, Calvin Plett, John W. M. Rogers
AUTOID
2005
IEEE
14 years 3 months ago
A Low Power and High Performance Analog Front End for Passive RFID Transponder
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, amo...
Jianyun Hu, Hao Min
VTC
2006
IEEE
134views Communications» more  VTC 2006»
14 years 3 months ago
Ultra Low-Power Digital Demodulators for Short Range Applications
— In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that uses limiter amplifier (i...
Mehmet R. Yuce, Ahmet Tekin
ISVLSI
2006
IEEE
137views VLSI» more  ISVLSI 2006»
14 years 3 months ago
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems
This paper presents the low power implementation of a Maximum Likelihood (ML) based detector used in the receiver part of a Multiple Input and Multiple Output (MIMO) systems. Low ...
T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J....
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
14 years 3 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
ICMCS
2006
IEEE
204views Multimedia» more  ICMCS 2006»
14 years 3 months ago
Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder
Low power hardware design for entropy coding of H.264/AVC baseline profile encoder is urgent for the increasing mobile applications. However, previous works are poor in the power...
Chuan-Yung Tsai, Tung-Chien Chen, Liang-Gee Chen
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 3 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...