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ASPDAC
2007
ACM
115views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware
- This paper covers a multi-functional hardware intellectual property (IP) for the encoding and decoding of digital moving pictures with low power consumption. The IP is mainly int...
M. Hase, K. Akie, M. Nobori, K. Matsumoto
ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
13 years 8 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
13 years 9 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
COMPCON
1994
IEEE
13 years 9 months ago
Low Power Hardware for a High Performance PDA
The first product in the Newton family operates under severe constraints in the areas of performance, cost, heat dissipation, power consumption, scalability, size and weight. This...
Michael Culbert
ISLPED
1996
ACM
101views Hardware» more  ISLPED 1996»
13 years 9 months ago
High-level power estimation
The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encourag...
Paul E. Landman
ISLPED
1996
ACM
100views Hardware» more  ISLPED 1996»
13 years 9 months ago
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods...
Tohru Ishihara, Hiroto Yasuura
DAC
1996
ACM
13 years 9 months ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
DAC
1996
ACM
13 years 9 months ago
POSE: Power Optimization and Synthesis Environment
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an enviro...
Sasan Iman, Massoud Pedram
ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
13 years 9 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
ICCAD
1996
IEEE
77views Hardware» more  ICCAD 1996»
13 years 9 months ago
Power optimization in disk-based real-time application specific systems
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
Inki Hong, Miodrag Potkonjak