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ISPD
1997
ACM
142views Hardware» more  ISPD 1997»
13 years 9 months ago
Minimization of chip size and power consumption of high-speed VLSI buffers
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
D. Zhou, X. Y. Liu
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
13 years 9 months ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding
ISLPED
1997
ACM
85views Hardware» more  ISLPED 1997»
13 years 9 months ago
Low power motion estimation design using adaptive pixel truncation
Power consumption is very critical for portable video applications such as portable video-phone. Motion estimation in the video encoder requires huge amount of computation and hen...
Zhong-Li He, Kai-Keung Chan, Chi-Ying Tsui, Ming L...
ISLPED
1997
ACM
108views Hardware» more  ISLPED 1997»
13 years 9 months ago
Analogue LSI RF switch and beamforming matrixes for communications satellites
Communications satellites use steerable antenna arrays for their communication links. These arrays need multi channel signal routing circuits up to several tens of channels. Tradi...
Markku Åberg, Anssi Leppänen, Arto Rant...
VTS
1998
IEEE
124views Hardware» more  VTS 1998»
13 years 9 months ago
A Test Pattern Generation Methodology for Low-Power Consumption
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
ICCAD
1998
IEEE
107views Hardware» more  ICCAD 1998»
13 years 9 months ago
Techniques for energy minimization of communication pipelines
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
Gang Qu, Miodrag Potkonjak
ITC
1999
IEEE
78views Hardware» more  ITC 1999»
13 years 9 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich
ISCAS
1999
IEEE
74views Hardware» more  ISCAS 1999»
13 years 9 months ago
A low-power switched-current algorithmic A/D converter
This paper reports the development of a low-power switchedcurrent algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter u...
A. Tezel, T. Akin
ISCAS
1999
IEEE
77views Hardware» more  ISCAS 1999»
13 years 9 months ago
Power reduction through iterative gate sizing and voltage scaling
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, W...
ICCAD
1999
IEEE
92views Hardware» more  ICCAD 1999»
13 years 9 months ago
Interface and cache power exploration for core-based embedded system design
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
Tony Givargis, Jörg Henkel, Frank Vahid