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ITC
1994
IEEE
111views Hardware» more  ITC 1994»
13 years 8 months ago
Simulation Results of an Efficient Defect-Analysis Procedure
For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavi...
Olaf Stern, Hans-Joachim Wunderlich
ITC
1993
IEEE
110views Hardware» more  ITC 1993»
13 years 8 months ago
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...
SIGSOFT
1998
ACM
13 years 8 months ago
Further Empirical Studies of Test Effectiveness
This paper reports on an empirical evaluation of the fault-detecting ability of two white-box software testing techniques: decision coverage (branch testing) and the all-uses data...
Phyllis G. Frankl, Oleg Iakounenko
ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
13 years 8 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
ITC
2000
IEEE
93views Hardware» more  ITC 2000»
13 years 9 months ago
Stuck-fault tests vs. actual defects
This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and comp...
Edward J. McCluskey, Chao-Wen Tseng
GLVLSI
2002
IEEE
98views VLSI» more  GLVLSI 2002»
13 years 9 months ago
Minimizing concurrent test time in SoC's by balancing resource usage
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
13 years 9 months ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov
ITC
2003
IEEE
177views Hardware» more  ITC 2003»
13 years 9 months ago
Analyzing the Effectiveness of Multiple-Detect Test Sets
Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensit...
R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Aniru...
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
13 years 9 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
ICTAC
2004
Springer
13 years 10 months ago
Minimal Spanning Set for Coverage Testing of Interactive Systems
A model-based approach for minimization of test sets for interactive systems is introduced. Test cases are efficiently generated and selected to cover the behavioral model and the ...
Fevzi Belli, Christof J. Budnik