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VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 5 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
VLSID
2007
IEEE
112views VLSI» more  VLSID 2007»
14 years 5 months ago
Synthesizing "Verification Aware" Models: Why and How?
Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazu...
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 5 months ago
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips
Recent advances in microfluidics technology have led to the emergence of miniaturized biochip devices for biochemical analysis. A promising category of microfluidic biochips relie...
Tao Xu, Krishnendu Chakrabarty, Fei Su
VLSID
2007
IEEE
85views VLSI» more  VLSID 2007»
14 years 5 months ago
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
Elias Kougianos, Saraju P. Mohanty
VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
14 years 5 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
14 years 5 months ago
Spectral RTL Test Generation for Microprocessors
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Nitin Yogi, Vishwani D. Agrawal
VLSID
2007
IEEE
209views VLSI» more  VLSID 2007»
14 years 5 months ago
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
Saraju P. Mohanty, Elias Kougianos
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 5 months ago
Interframe Bus Encoding Technique for Low Power Video Compression
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 5 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
VLSID
2007
IEEE
94views VLSI» more  VLSID 2007»
14 years 5 months ago
A Reduced Complexity Algorithm for Minimizing N-Detect Tests
? We give a new recursive rounding linear programming (LP) solution to the problem of N-detect test minimzation. This is a polynomialtime solution that closely approximates the exa...
Kalyana R. Kantipudi, Vishwani D. Agrawal