129
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EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level descripti...
123
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EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
We present a system for the formal veri cation of processors which combines a computer algebra simpli cation tool with an object-oriented approach. It has been successfully used f...
125
click to vote
EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets...
153
click to vote
EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...