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EURODAC
1995
IEEE
152views VHDL» more  EURODAC 1995»
15 years 8 months ago
Information model of a compound graph representation for system and architecture level design
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
Peter Conradi
EURODAC
1995
IEEE
138views VHDL» more  EURODAC 1995»
15 years 8 months ago
Reduced design time by load distribution with CAD framework methodology information
This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
EURODAC
1995
IEEE
202views VHDL» more  EURODAC 1995»
15 years 8 months ago
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems...
Santhanam Srinivasan, Niraj K. Jha
EURODAC
1995
IEEE
127views VHDL» more  EURODAC 1995»
15 years 8 months ago
Layout synthesis for datapath designs
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
EURODAC
1995
IEEE
173views VHDL» more  EURODAC 1995»
15 years 8 months ago
Cooperative concurrency control for design environments
In this paper, we present a new model for concurrency control that supports cooperation of design tools and designers in a design environment. We capture characteristic access and...
Ansgar Bredenfeld