Sciweavers

EURODAC
1995
IEEE
136views VHDL» more  EURODAC 1995»
15 years 8 months ago
Computing subsets of equivalence classes for large FSMs
Computing equivalence classes for FSMs has several applications to synthesis and veri cation problems. Symbolic traversal techniques are applicable to medium-small circuits. This ...
Gianpiero Cabodi, Stefano Quer, Paolo Camurati
EURODAC
1995
IEEE
116views VHDL» more  EURODAC 1995»
15 years 8 months ago
An improved relaxation approach for mixed system analysis with several simulation tools
: This paper introduces a modified relaxation approach that allows to improve the convergence of iterations while analyzing mixed systems with different simulators. The method redu...
Vladimir B. Dmitriev-Zdorov, Bernhard Klaassen
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
15 years 8 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
15 years 8 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
15 years 8 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...