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FPL
2006
Springer
96views Hardware» more  FPL 2006»
15 years 7 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
FPL
2006
Springer
91views Hardware» more  FPL 2006»
15 years 7 months ago
Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics
Ripple-carry architectures are the norm in today's reconfigurable fabrics. They are simple, require minimal routing, and are easily formed across arbitrary cells in a fabric....
Michael T. Frederick, Arun K. Somani
FPL
2006
Springer
123views Hardware» more  FPL 2006»
15 years 7 months ago
Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations
: FPGA-based acceleration of molecular dynamics (MD) has been the subject of several recent studies. Here we describe a new non-bonded force computation pipeline implemented on a 2...
Yongfeng Gu, Tom Van Court, Martin C. Herbordt
FPL
2006
Springer
137views Hardware» more  FPL 2006»
15 years 7 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 7 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...