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FPL
2006
Springer
103views Hardware» more  FPL 2006»
15 years 7 months ago
Modular Partitioning for Incremental Compilation
This paper presents an automated partitioning strategy to divide a design into a set of partitions based on design hierarchy information. While the primary objective is to use the...
Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry...
FPL
2006
Springer
140views Hardware» more  FPL 2006»
15 years 7 months ago
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
FPL
2006
Springer
99views Hardware» more  FPL 2006»
15 years 7 months ago
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...
Daniel Ziener, Stefan Assmus, Jürgen Teich
FPL
2006
Springer
66views Hardware» more  FPL 2006»
15 years 7 months ago
Minimizing Communication Cost for Reconfigurable Slot Modules
We discuss the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine (ESM). Bad placement of modules may deg...
Sándor P. Fekete, Jan van der Veen, Mateusz...
120
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FPL
2006
Springer
158views Hardware» more  FPL 2006»
15 years 7 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...