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ARC
2006
Springer
154views Hardware» more  ARC 2006»
15 years 7 months ago
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems
This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides...
Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart P...
112
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CGO
2004
IEEE
15 years 7 months ago
Software-Controlled Operand-Gating
Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method fo...
Ramon Canal, Antonio González, James E. Smi...
CGO
2004
IEEE
15 years 7 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
CGO
2004
IEEE
15 years 7 months ago
Probabilistic Predicate-Aware Modulo Scheduling
Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transforma...
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Da...
ARC
2006
Springer
131views Hardware» more  ARC 2006»
15 years 7 months ago
Implementation of LPM Address Generators on FPGAs
Abstract. We propose the multiple LUT cascade as a means to configure an ninput LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port g...
Hui Qin, Tsutomu Sasao, Jon T. Butler