Sciweavers

CF
2007
ACM
15 years 9 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
CF
2007
ACM
15 years 9 months ago
Reconfigurable hybrid interconnection for static and dynamic scientific applications
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
Shoaib Kamil, Ali Pinar, Daniel Gunter, Michael Li...
CF
2007
ACM
15 years 9 months ago
Fast compiler optimisation evaluation using code-feature based performance prediction
Performance tuning is an important and time consuming task which may have to be repeated for each new application and platform. Although iterative optimisation can automate this p...
Christophe Dubach, John Cavazos, Björn Franke...
CF
2007
ACM
15 years 9 months ago
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
Juan M. Cebrian, Juan L. Aragón, José...
CF
2007
ACM
15 years 9 months ago
Performance/area efficiency in chip multiprocessors with micro-caches
This paper proposes the use of very small instruction caches, called micro-caches (
Michela Becchi, Mark A. Franklin, Patrick Crowley